1. Technical Field of the Invention
This invention relates generally to data communication systems and more particularly to data and/or clock recovery circuits used within such communication systems.
2. Description of Related Art
Communication systems are known to transport large amounts of data between a plurality of end user devices, which, for example, include telephones, facsimile machines, computers, television sets, cellular telephones, personal digital assistants, etc. As is also known, such communication systems may be local area networks (LANS) and/or wide area networks (WANs) that are stand-alone communication systems or interconnected to other LANs and/or WANs as part of a public switched telephone network (PSTN), packet switched data network (PSDN), integrated service digital network (ISDN), the Internet, etc. As is further known, communication systems include a plurality of system equipment to facilitate the transporting of data. Such system equipment includes, but is not limited to, routers, switches, bridges, gateways, protocol converters, frame relays, private branch exchanges, etc.
The transportation of data within communication systems is typically governed by one or more standards that ensure the integrity of data conveyances and fairness of access for data conveyances. For example, there are a variety of Ethernet standards that govern serial transmissions within a communication system at data rates of 10 megabits per second, 100 megabits per second, 1 gigabit per second and beyond. Another standard, which is for fiber optic data conveyances, is Synchronous Optical NETwork (SONET) that provides a data rate of 10 gigabits per second. In accordance with such standards, many system components and end user devices of a communication system transport data via serial transmission paths. Internally, however, the system components and end user devices process data in a parallel manner. As such, each system component and end user device must receive the serial data and convert the serial data into parallel data without loss of information.
Accurate recovery of information from high-speed serial transmissions typically requires transceiver components to operate at clock rates that are equal to or higher than the rate of the received serial data, which, for today's high-speed systems, requires very high clock rates. Such high clock rates limit the usefulness of prior art clock and data recovery circuits since such clock and data recovery circuits require precise alignment of the received serial data with the high-speed clock to recover an embedded clock signal in the data stream and/or to recover the data, which is difficult to achieve using today's integrated circuit fabrication techniques. In addition, the high-speed serial data requires the clock and data recovery circuits to have a bandwidth wide enough to handle the high-speed serial data, which is also difficult to achieve using today's integrated circuit fabrication techniques.
As the demand for data throughput increases, so do the demands for a low bit error rate, high-speed serial transceivers (i.e., a transmitter and a receiver, where the receiver includes a clock and data recovery circuit). The increased throughput demands are pushing some current integrated circuit manufacturing processes to their operating limits, where integrated circuit processing limits (e.g., device parasitics, trace sizes, propagation delays, device sizes, etc.) and integrated circuit (IC) fabrication limits (e.g., IC layout, frequency response of the packaging, frequency response of bonding wires, etc.) limit the speed at which the high-speed serial transceiver, and particularly the clock and data recovery circuit, may operate without excessive jitter and/or noise.
As is further known, a data detection and/or clock recovery circuit (or clock and data recovery circuit) has a phase locked loop (PLL) topology. Many data detection and/or clock recovery circuits include a phase detector, a charge pump circuit, a loop filter, a voltage controlled oscillator, a feedback circuit, and a coarse locked loop to establish an initial frequency for the overall circuit. Once the coarse locked loop has established the initial frequency, it is disabled and the remaining components of the data detection and clock recovery circuit are activated.
In this mode, the phase detector determines phase differences between an incoming stream of data and a feedback signal. The phase detector also produces the recovered data from the incoming stream of data and a recovered clock. The charge pump circuit converts the phase differences produced by the phase detector into a current signal. The loop filter converts the current signal into a controlled voltage that is provided to the voltage controlled oscillator. The voltage controlled oscillator generates a recovered clock based on the control voltage. The feedback circuit produces the feedback signal by dividing the recovered clock by a divider value, which may be one.
The phase detector is generally implemented as a logic phase detection circuit that detects a phase difference between the incoming data stream and the feedback signal. While there are other embodiments of phase detectors, in particular, multiplying phase detectors, they are not used in data detection and/or clock recovery circuits because of the randomness of the incoming data stream. As is known, a multiplying phase detector requires its two inputs, i.e., a feedback signal and an input signal, to have transitions at every clock boundary to function properly. In other words, a multiplying phase detector requires that its input be non-random to function properly.
For high-speed applications that can provide non-random signals to the phase detector (e.g., a phase locked loop), multiplying phase detectors are preferred over logic gate phase detectors because they are faster and lower the overall gain requirement of the circuit.
Therefore, a need exists for a multiplying phase detector for use in a random data locked loop architecture.